The advent of Very Large Scale Integration (VLSI) technology has enabled integrated circuit manufacturers to develop ever more complex logic circuitry on ever-smaller areas of chip wafers. The increasing integration and logic complexity has led to rapid increases in circuit function and vast improvements in performance metrics. The fabrication of any complex integrated circuit device involves a series of process steps to develop transistors, capacitors, etc. on the silicon substrate, as well as a series of steps to apply metal layers (typically 2-4 to date) that form the necessary interconnections to provide the basic predefined logic functionality of the device. However, each new generation of circuit design initially exhibits problems or "bugs," and many circuit designs go through a series of debugs and logic enhancements before replacement with subsequent generation designs.
In cell-based integrated circuit design, for complex integrated circuits such as processors and the like, conventional metal-only repairs and upgrades use repair cells, which contain spare gates. Typically, these spare gate cells are randomly dispersed throughout the cells of the designed logic circuitry on the IC chip.
In many known spare gate designs, each spare gate cell includes a collection of transistors coupled together into a pre-defined logic gate, to thereby perform a certain function. The pre-defined spare gates can include gates having any of the functions common in logic gates (NAND, NOR, Inverter, flip-flop, etc.) that can be used in fixing function and timing errors using only metal interconnections to and among a selected number of spare gates. Using this debugging technique, the base set of logic components of the device does not change. Only the metal layers change to achieve the connections needed to add selected gates from the spare cells into the functional circuitry of the pre-defined logic. The inclusions of such spare gate cells within the chip layout enables logic changes, specifically by reconfiguring one or more of the spare gate resources to become part of the working logic of the IC chip. For a desired modification, engineers select a unique combination of gates, from available resources, which are expected to achieve a desired repair or enhancement of the overall logic function.
At present most such spare gate cells comprise relatively simple, single function gates. One class of such gates is combinatorial gates (AND, NAND, NOR, etc), and another class is sequential gates (flip-flops and the like). To facilitate the spare gate approach to debugging for processors or other complex integrated circuits, there is a need for maximum flexibility in the design of spare gate arrays. Single function spare gate cells, even if available in a wide variety of functions and in substantial numbers, may not provide sufficient flexibility to enable all desired logic changes, to debug a particular device or implement certain desired enhancements of the device.
Accordingly, there have been a number of recent suggestions to implement reconfigurable spare gates. For example, U.S. Pat. No. 5,592,107 to McDermott et al. suggests the use of a configurable NAND/NOR logic element in a spare gate cell; and related U.S. Pat. No. 5,568,067 to McDermott et al. suggests the use of a configurable XNOR/XOR logic element. Although somewhat configurable, by assertion or desertion of a control signal, this type of spare cell only provides limited design options because each spare cell includes only a single logic element having at most two possible configurations.
U.S. Pat. No. 5,959,905 to Payne suggests use of a gate array in repair cells, for performing metal-only functional repairs in a cell-based circuit layout design. The repair gate array consists of a group of uncommitted (not interconnected) transistors. A cluster of cells are formed in various locations within the cell-based IC circuit and can be coupled together to form logic function elements. However, this approach requires excessive effort to design the standard logic elements from the transistors of the gate array and excessive amounts of interconnection.
Accordingly, a need still exists for spare gate cells constructed of standard building-block circuits that can be easily configured to achieve a plurality of logic functions, without excessive design work and interconnection and can be readily added to the pre-defined logic circuitry of the operating IC device.
Commonly assigned U.S. Pat. No. 5,696,943 to Lee discusses the need for careful strategy in the design to spare gate cells on a complex IC device, in terms of the type, the location, and the format of the spare gate cells. The types of spare cells should include the most frequently used standard cells in the associated design, since they are most likely to be needed to fix any errors. The spare gates should be grouped with the timing sensitive blocks prior to the place-and-route phase of manufacture, so that they will be located near potential problem gates. Also, the spare gates should be formatted so that they can be easily connected to the problem gates without damaging the existing circuits. For instance, the inputs of spare gates should be tied to either a positive power supply potential or voltage VCC or a ground potential VSS by top layer metal, because as compared to polysilicon or low layer metal, top layer metal is much easier to locate and connect during the place-and-route interconnect processing. Lee also suggests top layer connection for the outputs of the spare gates.
Most current VLSI circuits are constructed with three metal layers. The top layer is metal 3, whereas the bottom level is metal 1. The top layer, metal 3, is exposed and therefore is the easiest to connect to or cut, for changes. Some newer designs even utilize a metal 4 layer, and future designs may add still higher layers. In the spare condition, the inputs of spare gates must be tied to a reference voltage on the chip (Lee), for example to VCC or VSS. In many spare gate cells constructed in the past, this connection would be made through the metal 1 layer. However, such an interconnection makes it difficult to cut the connection to VCC or VSS and reconnect the inputs of the spare gates as needed to implement the desired logic change. As noted, the commonly assigned Patent to Lee does recommend top metal layer connection for the spare gate ports. However, the Lee Patent deals specifically with an IC structure having only two metal layers, i.e. the top layer actually mentioned was only metal 2. Any spare gate strategy for more recent IC designs therefore should maintain a top layer interconnect format, to make the debugging process faster and more reliable.